XIPHEENS

Extended Integrated Processor for Hardware Emulation of Evolvable Neural Spiking Systems

The XIPHEENS project main purpose is to proof the industrial suitability of a HEENS-based ASIC (Application-Specific Integrated Circuit) executing a large-scale SNN operating in a multi-chip ring configuration. We target to rise the TRL of the HEENS technology from 4 to 6, seeking to confirm the innovation potential of this technology and to improve the capability to transfer it to industry.

Objectives

• To design, fabricate, and package an initial (slave) ASIC in the target CMOS technology, embedding a 16x16 PE array. The ASIC will be fully-functional as a slave node.
• To design, fabricate and package a final ASIC. It will embed up to four multiprocessor nodes and include master capabilities, limited to the fundamental ones, due to the project development time constraint.
• To test the ASICs and to evaluate the industrial benefit of the proposed system in terms of cost, performance and power consumption.
• To build and test a demonstrator based on a ring of chips. Final ASIC instances will be connected in a ring topology, including at least three chips, capable to emulate almost 25000 neurons executing SNN benchmarks.
• To evaluate the best valuation alternative. Registering a patent of the chip, creating a spinoff, or both, will be studied in the light of the obtained results.
• To acquire deep know-how and to train staff in advanced ASIC digital design.

Processing element detail

Coordinators:
Jordi Madrenas (jordi.madrenas@upc.edu)